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low noise, 1 ghz fastfet op amp s data sheet ada4817 - 1 / ada4817 - 2 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor fo r any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2008 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features high speed ?3 db bandwidth (g = 1, r l = 100 ): 1050 mhz slew rate: 87 0 v/s 0.1% settling time: 9 ns low input bias current: 2 pa low input capacitance common - mode capacitance: 1. 3 pf differential - mode capacitance: 0.1 pf low noise 4 nv/hz @ 10 0 khz 2.5 fa/hz @ 100 khz low distortion ?90 dbc @ 10 mhz (g = 1, r l = 1 k ) offset voltage: 2 mv max imum high output current: 4 0 ma supply current per amplifier : 19 ma power - down supply current per amplifier : 1 .5 ma applications p hotodiode amplifier s dat a acquisition front ends instrumentation filters adc driver s ccd output buffers connection diagram s nc = no connect 1 pd 2 fb 3 ?in 4 +in 7 out 8 +v s 6 nc 5 ?v s ada4817-1 top view (not to scale) 07756-001 figure 1. 8 - lead lfcsp (cp - 8- 2) fb 1 ?in 2 +in 3 ?v s 4 pd 8 +v s 7 out 6 nc 5 nc = no connect ada4817-1 top view (not to scale) 07756-002 figure 2. 8- lead soic (r d - 8- 1) 07756-003 1 ?in1 2 +in1 3 nc 4 ?v s2 1 1 nc 12 ?v s1 10 +in2 9 ?in2 5 out2 6 +v s2 7 pd2 8 fb2 fb1 +v s1 out1 15 16 14 13 ada4817-2 t op view (not to scale) nc = no connect pd1 figure 3. 16 - lead lf c s p (cp - 16 - 20 ) general description the ada4817 - 1 (single) and ada4817 - 2 (dual) fastfet ? amplifiers are unity - gain stable, ultra high speed voltage fee d back amplifiers with fet inputs. these amplifiers we re developed with the analog devices, inc. , proprietary e x tra fast complementary bipolar (xfcb) process , which allows the amplifiers to achieve ultra low noise (4 nv/hz; 2.5 fa/hz) as well as very high input impedances. with 1. 3 pf of input capacitance, low noise (4 nv/hz), low offset voltage (2 mv max imum ), and 1050 mhz ? 3 db band - width, the ada4817 - 1/ ada4871 - 2 are ideal for data acquisition front ends as well as wid e ba nd transimped ance applications, such as photodiode preamps. with a wide supply voltage range from 5 v to 10 v and the ability to operate on either single or dual supplies, the ada4817 - 1/ ada4817 - 2 are designed to work in a variety of applications including active filtering and adc driving. the ada4817 - 1 is available in a 3 mm 3 mm , 8 - lead lfcsp and 8 - lead soic , and the ada4817 - 2 is available in a 4 mm 4 mm , 16- lead lfc s p . these packages feature a low distortion pinout that improves second harmonic distortion and si m plifies circuit board layout. they also feature an e x posed paddle that provides a low thermal resistance path to the printed circuit board ( pcb ) . this enables more efficient heat transfer and i n creases reliability. these products are rated to work over the extended industrial te m perature range (? 40c to +105c).
ada4817- 1/ada4817 - 2 data sheet rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 connection diagrams ...................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 5 v operation ............................................................................. 3 5 v operation ............................................................................... 4 absolute maximum ratings ............................................................ 5 th ermal resistance ...................................................................... 5 maximum safe power dissipation ............................................. 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 8 test circuits ..................................................................................... 13 theory of operation ...................................................................... 14 closed - loop frequency response ........................................... 14 noninverting closed - loop freque ncy response .................. 14 inverting closed - loop frequency response ............................. 14 wideband operation ................................................................. 15 driving capacitive loads .......................................................... 15 thermal considerations ............................................................ 15 power - down operation ............................................................ 15 capacitive feedback ................................................................... 16 higher frequency attenuation ................................................. 16 layout, grounding, and bypassing consider ations .................. 17 signal routing ............................................................................. 17 power supply bypassing ............................................................ 17 grounding ................................................................................... 17 exposed paddle ........................................................................... 17 leakage currents ........................................................................ 18 input capacitance ...................................................................... 18 input - to - input/output coupling ............................................. 18 applications information .............................................................. 19 low distortion pinout ............................................................... 19 wideband photodiode preamp ................................................ 19 high speed jfet input instrumentation amplifier .............. 21 active low - pass filter (lpf) .................................................... 22 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 25 revision history 5 /13 rev. a to rev. b changes to figure 3 .......................................................................... 1 changes to figure 7 .......................................................................... 7 updated outline dimensions ....................................................... 2 4 changes to ordering guide .......................................................... 25 3 /0 9 rev. 0 to rev. a added 8 - lead soic package ............................................ universal changes to features section and general description section . 1 changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 4 changes to figure 4 .......................................................................... 5 changes to figure 9, figure 11, and figure 12 ............................. 8 changes to figure 21, figure 22, and figure 24 ......................... 10 changes to figure 33 ...................................................................... 12 added figure 34; renumbered sequentially .............................. 12 chan ges to thermal considerations section and power - down operation section ........................................................................... 15 changes to capacitive feedback section and figure 46 ........... 16 added higher frequency attenuation section , figure 47 , figure 48, and figure 49 ; renumbered sequentially ................. 16 updated outline di mensions ....................................................... 24 changes to ordering guide .......................................................... 25 11/0 8 revision 0 : initial version
data sheet ada4817- 1/ada4817 - 2 rev. b | page 3 of 28 specifications 5 v operation t a = 25c, +v s = 5 v, ? v s = ?5 v, g = 1 , r f = 348 ? for g > 1 , r l = 1 00 ? to ground, unless otherwise noted. table 1 . parameter conditions min typ max unit dynamic performance ? 3 db bandwidth v out = 0.1 v p -p 1050 mhz v out = 2 v p -p 2 00 mhz v out = 0.1 v p -p , g = 2 390 mhz gain bandwidth product v out = 0.1 v p -p 4 10 mhz full power bandwidth v in = 3.3 v p - p, g = 2 60 mhz 0.1 db flatness v out = 2 v p - p, r l = 10 0 ? , g = 2 6 0 mhz slew rate v out = 4 v step 870 v/s settli ng time to 0.1% v out = 2 v step , g = 2 9 ns noise/ harmonic per formance harmonic distortion ( hd2/hd3 ) f = 1 mhz, v out = 2 v p -p , r l = 1 k? ? 1 1 3 / ? 1 17 dbc f = 10 mhz, v out = 2 v p - p , r l = 1 k? ?9 0 /? 94 dbc f = 50 mhz, v out = 2 v p -p , r l = 1 k? ?64 /?66 dbc input voltage noise f = 100 khz 4 nv/hz input current noise f = 100 khz 2.5 fa/hz dc performance input offset voltage 0.4 2 mv input offset voltage drift 7 v/c input bias current 2 20 pa t min to t max 100 pa inp ut bias offset current 1 pa open - loop gain 62 6 5 db input characteristics input resistance common mode 500 g? input capacitance common mode 1. 3 pf differential mode 0.1 pf input common - mode voltage range ?v s to + v s ? 2. 8 v comm on - mode rejection v cm = 0.5 v ? 77 ? 90 db output characteri s tics output overdrive reco v ery time v in = 2. 5 v, g = 2 8 ns output voltage swing ?v s + 1.5 to + v s ? 1.5 ?v s + 1.4 to + v s ? 1.3 v r l = 1 k? ?v s + 1.1 to + v s ? 1.1 ?v s + 1 to + v s ? 1 v linear output current 1% output error 4 0 ma short - circuit current sinking/ s ourcing 100 /1 7 0 ma power - down pd pin voltage enabled >+v s ? 1 v powered d own <+v s ? 3 v turn - on/turn - off time 0.3/1 s input le akage current pd = +v s 0.3 3 a pd = ? v s 34 61 a power supply operating range 5 10 v quiescent current per amplifier 1 9 21 ma powered down quiescent current 1.5 3 ma positive power supply rejection +v s = 4. 5 v to 5.5 v , ?v s = ?5 v ? 67 ? 7 2 db negative power supply rejection +v s = 5 v, ?v s = ?4. 5 v to ?5.5 v ? 67 ? 7 2 db
ada4817- 1/ada4817 - 2 data sheet rev. b | page 4 of 28 5 v operation t a = 25c , + v s = 3 v, ? v s = ?2 v , g = 1, r f = 348 ? for g > 1, r l = 1 00 ? to ground , unless otherwise noted . table 2 . parameter conditions min typ max unit dynamic performance C 3 db bandwidth v out = 0.1 v p -p 500 mhz v out = 1 v p -p 160 mhz v out = 0. 1 v p - p , g = 2 280 mhz full power bandwidth v in = 1 v p - p, g = 2 95 mhz 0. 1 db flatness v out = 1 v p -p , g = 2 32 mhz slew rate v out = 2 v step 320 v/s settling time to 0.1% v out = 1 v step , g = 2 11 ns noise/ harmonic pe r formance harmonic distortion ( hd2/hd3 ) f = 1 mhz, v out = 1 v p -p , r l = 1 k ? ? 87/ ? 88 dbc f = 10 mhz, v out = 1 v p -p , r l = 1 k? ?68/? 66 dbc f = 50 mhz, v out = 1 v p -p , r l = 1 k? ?57/? 55 dbc input voltage noise f = 100 khz 4 nv/hz input current noise f = 100 khz 2.5 fa/hz dc performance input offset voltage 0.5 2. 3 mv input offset voltage drift 7 v/c input bias current 2 20 pa t min to t max 100 pa input bias offset current 1 pa open - loop gain 61 63 db input characteristics input resistance common mode 500 g? input capacitance common mode 1.3 pf differential mode 0.1 pf input common - mode voltage range ?v s to +v s ? 2.9 v common - mode rejection v cm = 0.25 v ? 72 ? 83 db output characteri s tics output overdrive reco v ery time v in = 1.25 v, g = 2 13 n s output v oltage swing r l = 100 ? ? v s + 1.3 to + v s ? 1.3 ? v s + 1 to +v s ? 1 . 2 v r l = 1 k? ?v s + 1 to +v s ? 1 . 1 ?v s + 0.9 to +v s ? 1 v linear output current 1% output error 20 ma short - circuit current sinking/ s ourcing 40/1 3 0 ma power - down pd pin voltage enabled >+v s ? 1 v powered d own <+v s ? 3 v turn - on/turn - off time 0.2/0.7 s input leakage current pd = +v s 0.2 3 a pd = ?v s 31 53 a power supply operating range 5 10 v quiescent current per amplifier 1 4 1 6 ma powered down quiescent current 1 .5 2. 8 ma positive power supply rejection +v s = 4.75 v to 5.25 v, ?v s = 0 v ? 66 ? 71 db negative power supply rejection +v s = 5 v, ?v s = ?0.25 v to + 0.25 v ? 63 ? 69 db
data sheet ada4817- 1/ada4817 - 2 rev. b | page 5 of 28 abso lute maximum ratings table 3 . parameter rating supply voltage 10.6 v power dissipation see figure 4 common - mode input voltage ?v s ? 0 .5 v to +v s + 0.5 v differential input voltage v s storage temperature range ?65c to +125c operating temperature range ?40c to +105c lead temperature (soldering , 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the de vice. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended perio ds may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is , ja is spec i fied for a device soldered in the circuit board for the surface - mount packages. table 4 . package type ja jc unit lfcsp _vd (ada4817 -1) 9 4 29 c/w soic _n_ep (ad a4817 - 1) 79 29 c/w lf c s p _w q (ada4817 - 2) 6 4 1 4 c/w maximum safe power dissipation the maximum safe power dissipation for the ada 4817- 1/ ada4817 - 2 are li m ited by the associated rise in junction temperature (t j ) on the die. at approximately 150 c ( which i s the glass transition te m perature) , the properties of the plastic change. even temporarily excee d ing this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ada 4817 - x . excee ding a junction temper a ture of 175 c for an extended perio d can result in changes in silicon devices, potentially causing degradation or loss of fun c tionality. the power dissipated in the package (p d ) is the sum of the qu i escent power dissipation and the power dissipated in the die due to the ada48 1 7 - 1 /ada4817 - 2 drive at the output. the quiescent power is the voltage between the supply pins (v s ) multiplied by the quiescent current (i s ). p d = quiescent power + ( total drive power C load power ) (1) ( ) l out l out s s s d r v r v v i v p 2 C 2 ? ? ? ? ? ? ? ? + = (2) consider rms output voltages. if r l is referenced to ?v s , as in single - supply oper a tion, the total drive power is v s i out . if the rms signal levels are indeterminate, consider the worst - case scenario , when v out = v s /4 for r l to mids upply. ( ) ( ) l s s s d r v i v p 2 4 / + = (3) in single - supply operation with r l referenced to ?v s , the worst - case situation is v out = v s /2. airflow increases heat dissipation, effectively reducing ja . m ore metal directly in contact with the package leads and e x pos ed paddle from metal traces , through holes, ground, and power planes also reduce s ja . figure 4 shows the maximum safe power dissipation in the package vs . the ambient te m perature for the exposed paddle lfcsp _vd ( s ingle 94c/w) , soic _n_ep (single 79 c/w) and lfcsp _ w q ( dual 64 c/w) package on a jedec standard 4 - layer board. ja values are approximations. 3.5 0 ?40 ambient temperature (c) maximum power dissipation (w) 3.0 2.5 2.0 1.5 1.0 0.5 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 ada4817-1, lfcsp ada4817-2, lfcsp 07756-008 ada4817-1, soic figure 4 . maximum safe power dissipation vs. ambient temperature for a 4- layer board esd caution
ada4817- 1/ada4817 - 2 data sheet rev. b | page 6 of 28 pin configurations a nd function d e scriptions 07756-005 nc = no connect 1 pd 2 fb 3 ?in 4 +in 7 out 8 +v s 6 nc 5 ?v s ada4817-1 top view (not to scale) notes 1. exposed p ad can be connected t o ground plane or neg a tive supp l y plane. figure 5 . ada4817 - 1 pin configuration (8 - lead lfcsp) table 5 . ada4817 - 1 pin function descriptions (8 - lead lfcsp) pin no. mnemonic descri ption 1 pd power - down. do not leave floating. 2 fb feedback pin. 3 ?in inverting input. 4 +in noninverting input. 5 ?v s negative supply. 6 nc no connect. 7 out output. 8 +v s positive supply. exposed pad (epad) exposed pad. can be connected to gnd, ?v s plane, or left floating. fb 1 ?in 2 +in 3 ?v s 4 pd 8 +v s 7 out 6 nc 5 nc = no connect ada4817-1 top view (not to scale) 07756-006 notes 1. exposed p ad can be connected t o ground plane or neg a tive supp l y plane. figure 6. ada4817 - 1 pin configuration (8 - lead soic) table 6 . ada4817 - 1 pin function descriptions (8 - lead soic) pin no. mnemonic description 1 fb feedback pin. 2 ?in inverting input. 3 +in noninverting input. 4 ?v s negative supply. 5 nc no connect. 6 out output. 7 +v s positive supply. 8 pd power - down. do not leave floating. exposed pad (epad) exposed pad. can be connected to gnd, ?v s plane, or left floating.
data sheet ada4817- 1/ada4817 - 2 rev. b | page 7 of 28 07756-107 nc = no connect notes 1. exposed pad can be connected to the ground plane or negative supply plane. 1 ?in1 2 +in1 3 nc 4 ?v s2 11 nc 12 ?v s1 10 +in2 9 ?in2 5 out2 6 +v s2 7 pd2 8 fb2 fb1 +v s1 out1 15 16 14 13 ada4817-2 top view (not to scale) pd1 figure 7 . ada4817 - 2 pin config uration (16 - lead lfcsp) table 7 . 16 - lead lfcsp pin function descriptions pin no. mnemonic description 1 ?in1 inverting input 1 . 2 +in1 noninverting input 1 . 3, 11 nc no connect . 4 ?v s2 negative supply 2 . 5 out2 output 2 . 6 + v s2 positive supply 2 . 7 pd2 power - down 2. do not leave floating. 8 fb2 feedback pin 2 . 9 ?in2 inverting input 2 . 10 +in2 noninverting input 2 . 12 ?v s1 negative supply 1 . 13 out1 output 1 . 14 +v s1 positive supply 1 . 15 pd1 powe r - down 1. do not leave floating. 16 fb1 feedback pin 1 . exposed p ad (epad) exposed pad. can be connected to gnd, ?v s p lane , or left floating.
ada4817-1/ada4817-2 data sheet rev. b | page 8 of 28 typical performance characteristics t a = 25c, v s = 5 v, g = 1, (r f = 348 for g > 1), r l = 100 to ground, small signal v out = 100 mv p-p, large signal v out = 2 v p-p, unless noted otherwise. 6 ?12 100k 10g normalized closed-loop gain (db) frequency (hz) 1m 10m 100m 1g 3 0 ?3 ?6 ?9 07756-066 g=1,single g=1,dual g = 2 g=5 figure 8. small signal frequency response for various gains (lfcsp) 6 ?12 100k 10g closed-loop gain (db) frequency (hz) 1m 10m 100m 1g 3 0 ?3 ?6 ?9 v s = 10v, lfcsp v s = 10v, soic 07756-007 v s =5v, lfcsp v s = 5v, soic figure 9. small signal frequency response for various supplies 9 ?9 100k 10g closed-loop gain (db) frequency (hz) 1m 10m 100m 1g 6 3 0 ?3 ?6 07756-068 c l =2.2pf c l =6.6pf c l =4.4pf c l =0pf g = 2 r f =274 ? figure 10. small signal frequency response for various c l ?12 100k 10g normalized closed-loop gain (db) frequency (hz) 1m 10m 100m 1g 6 3 0 ?3 ?6 ?9 07756-009 g = 2 g = 1, dual g = 5 g=1,single figure 11. large signal frequency response for various gains 6 ?12 100k 10g closed-loop gain (db) frequency (hz) 1m 10m 100m 1g 3 0 ?3 ?6 ?9 v s = 10v v s =5v 07756-010 v out = 1v p-p figure 12. large signal frequency response for various supplies 9 ?9 100k 10g closed-loop gain (db) frequency (hz) 1m 10m 100m 1g 6 3 0 ?3 ?6 07756-011 r f =274 ? r f = 348 ? r f = 200 ? g = 2 figure 13. small signal frequency response for various r f
data sheet ada4817-1/ada4817-2 rev. b | page 9 of 28 0.5 ?0.5 100k 10g normalized closed-loop gain (db) frequency (hz) 1m 10m 100m 1g 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 07756-012 g=2,ss g=2,ls g = 1, ls g=1,ss figure 14. 0.1 db flatness frequency response vs. gain and output voltage ? 20 ?140 100k 100m frequency (hz) distortion (dbc) ?40 ?60 ?80 ?100 ?120 1m 10m 07756-014 hd2, r l = 100 ? hd2, r l = 1k ? hd3, r l = 1k ? hd3, r l = 100 ? figure 15. distortion vs. frequency for various loads, v out = 2 v p-p ? 20 ?140 100k 100m frequency (hz) distortion (dbc) ?40 ?60 ?80 ?100 ?120 1m 10m 07756-016 hd3, v s = 10v hd3, v s = 5v hd2, v s = 10v hd2, v s = 5v figure 16. distortion vs. frequency for various supplies, g = 2, v out = 2 v p-p 6 3 0 ?3 ?6 ?9 ?12 100k 1m 10m 100m 1g 10g closed-loop gain (db) frequency (hz) 07756-036 t a = +25c, single t a = +25c, dual t a = ?40c, single t a = ?40c, dual t a = +105c, single t a = +105c, dual figure 17. small signal frequency response vs. temperature ? 20 ?140 100k 100m frequency (hz) distortion (dbc) ?40 ?60 ?80 ?100 ?120 1m 10m 07756-013 hd2, v s = 10v hd3, v s = 10v hd2, v s = 5v hd3, v s = 5v figure 18. distortion vs. frequency for various supplies, v out = 2 v p-p ? 20 ?140 06 output voltage (v p-p) distortion (dbc) ?40 ?60 ?80 ?100 ?120 12345 07756-017 hd2, r l = 100 ? f c = 1mhz hd2, r l = 1k ? hd3, r l = 100 ? hd3, r l = 1k ? figure 19. distortion vs. output voltage for various loads
ada4817-1/ada4817-2 data sheet rev. b | page 10 of 28 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 output voltage (v) time (5ns/div) 07756-018 dual single dual, c f = 0.5pf single, no c f g = 2 figure 20. small signal transient response 0.075 0.050 0.025 0 ?0.025 ?0.050 ?0.075 output voltage (v) time (5ns/div) 07756-022 single, soic r f = 0 ? r l = 100 ? v s = 5v g = +1 dual, lfcsp single, lfcsp figure 21. small signal transient response vs. package 6 ?6 time (10ns/div) output voltage (v) 4 2 0 ?2 ?4 2 v in 07756-019 g = 2 v out figure 22. output overdrive recovery 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 output voltage (v) time (5ns/div) 07756-021 dual single dual, c f = 0.5pf single, no c f v s = 5v g = 2 figure 23. small signal transient response 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 output voltage (v) time (5ns/div) 07756-024 dual, lfcsp r f = 0 ? r l = 100 ? v s = 5v g = +1 single,soic single, lfcsp figure 24. large signal transient response 0.5 0.4 0.3 0.2 0.1 0 ?0.3 ?0.2 ?0.1 ?0.4 ?0.5 settling time (%) time (5ns/div) 07756-023 settling time figure 25. 0.1% short-term settling time
data sheet ada4817- 1/ada4817 - 2 rev. b | page 11 of 28 0 ?100 100k 1g frequency (hz) psrr (db) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 1m 10m 100m 07756-032 ?psrr +psrr figure 26 . psrr vs. frequency ?20 ?25 ?30 ?35 ?40 ?45 ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 100k 1m 10m 100m 1g cmrr (db) frequency (hz) 07756-029 figure 27 . cmrr vs. f requency 100 0.01 100k 1g 100m 10m 1m output impedance (?) frequency (hz) 10 1 0.1 07756-030 figure 28 . output impedance vs. frequency 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?40 ?20 0 20 40 60 80 100 offset voltage (mv) temperature (c) 07756-037 figure 29 . offset voltage vs. temperature 1000 1 10 100m frequency (hz) input voltage noise (nv/ hz) 100 1k 10k 100k 1m 10m 10 100 07756-026 figure 30 . input voltage noise 24 22 20 18 16 14 12 10 ?40 ?20 0 20 40 60 80 100 supply current (ma) temperature (c) 07756-033 v s = 5v v s = +5v figure 31 . qui escent current vs. temperature for various supply voltages
ada4817-1/ada4817-2 data sheet rev. b | page 12 of 28 1.6 1.4 1.5 1.3 1.2 1.1 1.0 0.9 0.8 ?40 ?20 0 20 40 60 80 100 output saturation voltage (v) temperature (c) 07756-034 - v s = 5v v s = +5v ?v s + v out ?v s + v out +v s ? v out +v s ? v out r l = 100 ? figure 32. output saturation voltage vs. temperature 07756-015 70 60 50 40 30 20 10 0 0 ?45 ?90 ?135 ?180 ?10 10k 100k 1m 10m 100m 1g phase (degrees) gain (db) frequency (hz) gain phase figure 33. open-loop gain and phase vs. frequency 800 600 700 500 400 300 200 100 0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 number of hits v os (mv) 07756-025 n: 4197 mean: ?0.0248457 sd: 0.245658 figure 34. input offset voltage histogram
data sheet ada4817- 1/ada4817 - 2 rev. b | page 13 of 28 test circuits t he output feedback pin s are used for ease of layout as shown in figure 35 to figure 40. v in v out 0.1f 0.1f 0.1f 10f +v s ?v s 49.9? r l + 10f + 07756-147 figure 35 . g = 1 configuration v out 0.1f 49.9? +v s ?v s r l 10f + ac 07756-145 figure 36 . positive power supply rejection v in v out 0.1f 0.1f 10f +v s ?v s 49.9? r l 0.1f c l + 10f + r f r snub r g 07756-142 figure 37 . capacitive load configuration v in v out 0.1f 0.1f 0.1f 10f +v s ?v s 49.9? r l + 10f + r f r g 07756-141 figure 38 . noninverting gain configuration 0.1f v out +v s ?v s r l 10f + ac 49.9? 07756-148 figur e 39 . negative power supply rejection v in v out 0.1f 0.1f 0.1f 10f +v s ?v s 1k? 1k? 1k? 1k? 53.6? r l + 10f + 07756-146 figure 40 . common - mode rejection
ada4817- 1/ada4817 - 2 data sheet rev. b | page 14 of 28 theory of operation the ada4817 - 1/ada4817 - 2 are voltage feedback operational amplifier s that combine new architecture for fet i nput operational amplifiers with the extra f ast c omplementary b ipolar (xfcb) process from analog devices , resulting in an outstanding combination of speed and low noise. the innovative high speed fet input stage handles common - mode signals from the negativ e supply to within 2. 7 v of the positive rail. this stage is combined with an h - bridge to attain a 87 0 v/s slew rate and low distortion, in addition to 4 nv/hz input voltage noise. t he a mplifier features a high speed output stage capable of driving heavy loads sourcing and sinking up to 4 0 ma of linear current . supply current and offset current are laser trimmed for optimum performance. these specifications make the ada4817 - 1/ ada4817 - 2 a great choice for high speed instrumentation and high resolution dat a acquisition systems. its low noise, p icoamp input current, precision offset, and high speed make them superb preamps for fast photo - diode applications. closed - loop frequency respo nse the ada4817 - 1/ada4817 - 2 are classic voltage feedback amplifier s with an open - loop frequency response that can be approximated as the integrator response shown in figure 43 . basic closed - loop frequency response for inverting and noninverting configurations can be derived from the schem atics shown in figure 41 and figure 42. r f a v out r g v in v e 07756-044 figure 41 . noninverting configuration r f v e a v out r g v in 07756-045 figure 42 . inverting configuration no ninverting closed - loop frequency response solving for the transfer function , ( ) ( ) g crossover g f f g crossover i o r f s r r r r f v v + + + = 2 2 (4) where f crossover is the frequency where the amplif iers open - loop gain equals 0 db. at dc , g g f i o r r r v v + = (5) closed - loop ?3 db frequency g f g crossover 3db r r r f f + = ? (6) inverting closed - loop frequency respo nse solving for the transfer function , ( ) g crossover g f f crossover i o r f s r r r f v v + + ? = 2 2 (7) at dc g f i o r r v v ? = (8) solve for c losed - loop ?3 db frequency by, g f g crossover db r r r f f + = ? 3 (9) frequency (mhz) 80 60 0.1 1000 open-loop gain (a) (db) 1 100 10 40 20 0 f crossover = 410mhz a = (2 ? f crossover )/s 07756-046 figure 43 . open - loop gain vs. frequency and basic connections the closed - loop bandwidth is inversely proportional to the noise gain of the op amp circuit, (r f + r g )/r g . this simple model is accurate for noise gains above 2. the actual bandwidth of circ uits with noise gains at or below 2 is higher than those predicted with this model due to the influence of other poles in the frequency response of the real op amp. figure 44 s hows a voltage feedback amplifiers dc errors. for both inverting and noninverting configurations , ( ) ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? ? + = ? + g f g os f b g f g s b out r r r v r i r r r r i error v (10) r f a r g i b ? r s i b + +v os ? 07756-047 v out v in figure 44 . voltage feedback amplifiers dc errors
data sheet ada4817- 1/ada4817 - 2 rev. b | page 15 of 28 the voltage error due to i b+ and i b C is minimized if r s = r f || r g (though with the ada48 17- 1/ada4817 - 2 input currents in the p ico amp range, this is likely not a concern). to include com mon - mode effects and power supply rejection effects, total v os can be modeled by cmr v psr v v v cm s nom os os + + = (11) w here: nom os v is the offset vol tage specified at nominal conditions . v s is the change in power supply from nominal conditions. psr is the power supply rejection . v cm is the change in common - mode v oltage from nominal conditions. cmr is the common - mode rejection. wideband operation the ada4817 - 1/ada4817 - 2 provides excellent performance as a high speed buffer. figure 41 shows the circuit used for wideband characterization for high gains. the impedance at the summing junction (r f || r g ) forms a pol e in the loop response of the amp - lifier with the amplifiers input capacitance of 1. 3 pf. this pole can cause peaking and ringing if its frequency is too low. feed - back resistances of 100 ? to 400 ? are recommended because they minimize the peaking and they do not degrade the performance of the output stage. peaking in the frequency response can also be compensated for with a small feedback capacitor (c f ) in parallel with the feedback r esistor, or a series resistor in the noninverting input , as shown in figure 45. the distortion performance depends on a number of variables: ? the closed - loop gain of the application ? whether it is inverting or noninv erting ? amplifier loading ? signal frequency and amplitude ? board layout the best performance is usually obtained in the g + 1 configuration with no feedback resistance, big output load resistors , and small board parasitic capacitances. driving capacitive l oa ds in general, high speed amplifiers have a difficult time driving capacitive loads. this is particularly true in low closed - loop gains, where the phase margin is the lowest. the difficulty arises because the load capacitance, c l , forms a pole with the ou tput r esistance, r o , of the amplifier. the pole can be descri bed by the following equ a tion : l o p c r f 2 1 = (12) if this pole occurs too close to the unity - gain crossover point, the phase margin d e grades. this is due to the additional phase loss as sociated with the pole. note that such capacitance introduce s significant peaking in the frequency response. larger capacitance values can be driven but must use a snubbing resi s tor (r snub ) at the output of the ampli fier, as shown in figure 45 . adding a small series resistor, r snub , creates a zero that cancels the pole introduced by the load c a pacitance. typical values for r snub can r ange from 10 ? to 50 ?. the value is typically based on the circuit r e quirements. figure 45 also shows another way to reduce the effect of the pole created by the capacitive load (c l ) by plac ing a capacitor (c f ) in the feedbac k loop parallel to the feedback resistor typical capacitor values can range from 0.5 pf to 2 pf . figure 46 shows the effect of adding a feedback capacitor to the frequency response. v in v out 0.1f 0.1f 10f +v s ?v s ? r l 0.1f c l + 10f + r f r snub c f r g 07756-143 figure 45 . r snub or c f used to reduce peaking thermal consideratio ns with 10 v power supplies and 19 ma quiescent current, the ada4817 - 1/ada4817 - 2 dissipate 190 mw with no load. this implies that in the lfcsp, whose thermal resistance is 94 c/w for the ada481 7 - 1 and 64 c/w for the ada4817 - 2 , th e junction temperature is typically almost 25 higher than the ambient tem - perature . the ada4817 - 1/ada4817 - 2 are designed to maintain a cons tant bandwidth over temperature; therefore, an initial ramp up of the current co nsumption during warm - up is expected. the v os t emperature drift is below 8 v/c; therefore, it can change up to 0.3 mv due to warm - up effects for an ada4817 - 1/ada4817 - 2 in a lfcsp on 10 v. the input bias current increases by a factor of 1.7 for every 10c rise in temperature. heavy loads increase power dissipation and raise the chip junction temperature as described in the absolute maximum ratings section. take care not to exceed the rated power dissipation of the package. power - d own operation the ada4817 - 1/ada4817 - 2 are equipped with separate power - down pin s ( pd ) for each amplifier. this allows the user the ability to reduce the quiescent supply current when an amplifier is inactive from 19 ma to below 2 ma. the power - down threshold levels are derived from the voltage applied to the +v s pin. in 5 v supply application, the enable voltage is greater than +4 v, and in a + 3 v , ?2 v supply application, the enable voltage is greater than +2 v. however, t he amplifier is powered down whenever the voltage applied to pd is 3 v below +v s . if the pd pin is not used, connect it to the positive supply to ensure proper start - up .
ada4817- 1/ada4817 - 2 data sheet rev. b | page 16 of 28 table 8 . power - down voltage control pd pin 5 v +3 v, ? 2 v not active >4 v >2 v active <2 v <0 v capacitive feedback due t o package variations and pin - to - pin parasitic s between the single and the dual models , the ada4817 - 2 has a little more peaking then the ada4817 - 1 , especially at a gain of 2. the best wa y to tame the peaking is to place a feedback capacitor across the feedback resistor. figure 46 shows the small signal frequency response of the ada4817 - 2 at a gain of 2 vs. c f . at first , no c f was used to show the peaking , but then two other values of 0.5 pf and 1 pf were used to show how to reduce the peaking or even eliminate it. as shown in figure 46 , if the power consumption is a factor in the system, then using a larger feedback capacitor is acceptable as long as a feedback capacitor is used across it to control the peaking. however, if power consumption is not an issue, then a lower value feedback resistor, such as 200 ?, would not require any additional feedback capaci tance to maintain flatness and lower peaking. 9 6 3 0 ?3 ?6 ?9 1m 10m 100m 1g 10g closed-loop gain (db) frequency (hz) 07756-049 r f = 348 g = 2 v s = 10v v out = 100mv p-p r l = 100 c f = 1pf c f = 0.5pf no c f figure 46 . small signal frequency response vs. feedback capacitor (ada4817 - 2) higher frequency att enuation there is a nother package variation problem between the soic and the lfcsp p ackage . the soic package shows approximately 1 db to 1.5 db of additional peaking at a gain of 1 . this is due to the parasitic in the soic package, which is not recommended for very high frequency parts that exceed 1 ghz. a good approach to reduc ing the pe aking is to place a resistor , r s , in series with the noninverting input. t his create s a first - order pole formed by r s and c in , the com mon - mode input capacitance. figure 47 shows the higher frequency attenua tion, which reduces the peaking but also reduces the ? 3 db bandwidth. ?9 ?6 ?3 0 3 6 1m 10m 100m 1g 10g closed-loop gain (db) frequency (hz) r s = 100? r s = 75? r s = 50? r s = 0? 07756-247 r l = 100 v s = 5v v out = 0.1v p-p g = 1 figure 47 . small signal frequency response for various r s (soic) as shown in figure 47 , the peaking dropped by almost 2 db when r s = 0 ? to r s = 100 ?, and in return, the ? 3 db bandwidth dropped from 1 ghz to 700 mhz. to maintain the ? 3 db bandwidth and to reduce peaking , an rlc circuit is recommend ed instead of r s , as shown in figure 48. l 10nh r 120? c 2pf 07756-248 figure 48 . rlc c ircuit the r in parallel to the series lc form s a notch that can be shaped to compensate for the peak ing produced by the amplifier. th e result is a smooth 1 ghz ? 3 db bandwidth , 250 mhz 0.1 db flatness , and less than 1 db of peaking. t his circuit should be placed in the path of the noninverting input when the ada4817 - x is used at a gain of 1. the rlc values m ay need tweaking depending on the source impedance and the flatness and band - width required. figure 49 shows the frequency response after the rlc circuit is in place. ?9 ?6 ?3 0 3 6 1m 10m 100m 1g 10g closed-loop gain (db) frequency (hz) rlc no rlc 07756-249 r l = 100 v s = 10v v out = 100mv p-p g = 1 figure 49 . frequency response with rlc circuit
data sheet ada4817- 1/ada4817 - 2 rev. b | page 17 of 28 layout, grounding, a nd bypassing conside rations laying out the pcb is usually the last ste p in the design process and oft en proves to be one of the most critical. a brilliant design can be rendered useless b e cause of poor layout. because the ada4817 - 1/ada4817 - 2 can operate into the rf frequency spectrum, high frequency board layout co n siderations must be taken into account. the pcb layout, signal routing, power supply bypassing , and grounding all must be a d dressed to ensure optimal performance. signal routing the ada4817 - 1/ada4817 - 2 feature the new low distortion pinout w ith a dedicated feedback pin that allows a compact la y out. the dedicated feedback pin reduces the distance from the ou t put to the inverting input, which greatly simplifies the routing of the feedback ne t work. when laying out the ada4817 - 1/ada4817 - 2 as a unity - gain amplifier, it is recommended that a short, b ut wide, trace be placed between the ded i cated feedback pin s, and the inverting input to the amplifier be used to minimize stray parasitic inductance. to minimize parasitic inductances, use ground planes under high frequency signal traces. however, remove the ground plane from under the input and output pins to mi nimize the formation of parasitic capacitors, which degrade s phase margin. signals that are suscept i ble to noise pickup should be run on the internal layers of the pcb, which can provide maximum shiel d ing. power supply bypassi ng power supply bypassing is a critical aspect of the pcb design process. for best performance, the ada4817 - 1/ada4817 - 2 power supply pins need to be properly bypassed. a parallel connection of capacitors from each of the pow er su p ply pins to ground works best. paralleling different values and sizes of capacitors helps to ensure that the power sup ply pins see a low ac impedance across a wide band of freque n cies. this is important for minimizing the coupling of noise into the a mpl i fier. starting directly at the power supply pins, place the smallest value and sized component on the same side of the board as the amplifier, and as close as possible to the amplifier, and connect it to the ground plane. repeat t his pro c ess for the ne xt large st value capacitor. it is re c ommended that a 0.1 f ceramic , 0508 case be used for the ada4817 - 1/ada4817 - 2 . the 0508 offers low series inductance and excellent high freque ncy performance. the 0.1 f provides low imp edance at high frequencies. plac e a 10 f electrolytic capac i tor in par allel with the 0.1 f. the 10 f capacitor pr o vides low ac impedance at low frequencies. smaller values of electrolytic capacitors can be used depending on the circuit requirements. additional smaller value capacitors help to pr o vide a low impedance path for unwanted noise out to higher freque n cies but are not always necessary. placement of the capacitor retu rns (grounds) is also important. r e turning the capacitors grounds close to the amplifier load is critical for d istortion performance. keeping the capacitors di s tance short but equal from the load is optimal for perform ance. in some cases, bypassing between the two supplies can help to i m prove psrr and to maintain distortion performance in crowded or difficult layo uts. this is another option to improve performance. minimizing the trace length and widening the trace from the capacitors to the amplifier reduce s the trace inductance. a series inductance with the parallel capacitance can form a tank circuit, which can introduce high frequency ringing at the output. this addition al inductance can also contribute to increased disto r ti on due to high frequency compression at the output. the use of vias should be min i mized in the direct path to the amplifier power supply pin s because vias can introduce parasitic indu c tance, which can lead to instability. when required to use vias, choose mult i ple large diameter vias because this lowers the equivalent parasitic indu c tance. grounding the use of ground and power planes is encour aged as a method of prov iding low impedance returns for power supply and signal cu rrents. ground and power planes can also help to reduce str ay trace inductance and to provide a low thermal path for the a m plifier. do not use g round and power planes under a ny of the pins . the mounting pads and the ground or power planes can form a parasitic capacitance at the input of the amplif i er . stray capacitance on the inverting input and the fee d back resistor form a pole, which degrades the phase margin, leading to i nstability. e x cessive stray capacitance on the output also forms a pole, which degrades phase margin. exposed paddle the ada4817 - 1/ada4817 - 2 feature an exposed paddle, which lowers the thermal resistance by 25% compared to a standard soic plastic package. the exposed paddle of the ada4817 - 1 / ada4817 - 2 float s internally which provides the maximum flexibility and ease of use. it can be connected to the ground plane or to the negative power supply p lane . in case s where thermal heating is not an issue, the expo sed pad c an be left floating. the use of thermal vias or heat pipes can also be incorp o rated into the design of the mounting pad for the exposed pa d dle. these additional vias help to lower the overall jun c tion - to - ambient temperature ( ja ). using a heavier weight copper on the surface to which the exposed paddle of the amplifier is soldered can greatly reduce the ov erall thermal resistance seen by the ada4817 - 1/ada4817 - 2 .
ada4817- 1/ada4817 - 2 data sheet rev. b | page 18 of 28 leakage currents poor pc b layout, contaminants, and the boa rd insulator material can create leakage currents that are much larger than the input bias current of the ada4817 - 1/ada4817 - 2 . any voltage differential between the inputs and nearby runs sets up leakage currents through the pc b insulator, for example, 1 v / 100 g? = 10 pa. similarly, any contaminants , such as skin oils on the board , can create significant leakage . to reduce leakage significantly, put a guard ring (shield) around the inputs and input leads that are driven to the same voltage potential as the input s. this way there is no voltage potential between the inputs and surrounding area to set up any leakage currents. for the guard ring to be completely effective, it must be driven by a relatively low impedance source and should completely surround th e input leads on all sides ( above and below ) while using a multilayer board. another effect that can cause leakage currents is the charge abso rption of the insulator material itself. minimizing the amo unt of material between the input leads and the guard ring he lps to reduce the absorption. in addition , low absorption materials, such as teflon ? or ceramic, can be necessary in some instances. input capacitance along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. a few picofarad s of capacitance reduces the input impedance at high frequencies, in turn increasing the gain of the amplifier , causing peaking of the frequency response or even oscillations if severe enough. it is recommended that t he external passive components connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance. the ground and power planes must be kept at a small distance from the input pins on all layers of the board. input - to - in put/ output coupling to minimize capacitive coupling between the inputs and output s , the output signal traces should not be parallel with the inputs. in addition, the input traces should not be close to each other. a minimum of 7 mils between the two input s is recommended.
data sheet ada4817-1/ada4817-2 rev. b | page 19 of 28 applications information low distortion pinout the ada4817-1/ada4817-2 feature a new low distortion pinout from analog devices. the new pinout provides two advantages over the traditional pinout. the first advantage is improved second harmonic distortion performance, which is accomplished by the physical separation of the noninverting input pin and the negative power supply pin. the second advantage is the simplification of the layout due to the dedicated feedback pin and easy routing of the gain set resistor back to the inverting input pin. this allows a compact layout, which helps to minimize parasitics and increase stability. the designer does not need to use the dedicated feedback pin to provide feedback for the ada4817-1/ada4817-2. the output pin of the ada4817-1/ada4817-2 can still be used to provide feedback to the inverting input of the ada4817-1/ada4817-2. wideband photodiode preamp the wide bandwidth and low noise of the ada4817-1/ ada4817-2 make it an ideal choice for transimpedance amplifiers, such as those used for signal conditioning with high speed photodiodes. figure 50 shows an i/v converter with an electrical model of a photodiode. the basic transfer function is ff f photo out rsc ri v ? ? ? 1 (13) where: i photo is the output current of the photodiode. the parallel combination of r f and c f sets the signal bandwidth. r sh = 10 11 ? r f c f c m c m c d c s v b i photo 07756-048 v out figure 50. wideband photodiode preamp the stable bandwidth attainable wi th this preamp is a function of r f , the gain bandwidth product of the amplifier, and the total capacitance at the summing junction of the amplifier, including the photodiode capacitance (c s ) and the amplifier input capacitance. r f and the total capacitance produce a pole in the amplifiers loop transmission that can result in peaking and instability. adding c f creates a zero in the loop transmission that compen- sates for the effect of the pole and reduces the signal bandwidth. it can be shown that the signal bandwidth obtained with a 45 phase margin (f (45) ) is defined by ) (2 )45( dm s f cr cccr f f ????? ? (14) where: f cr is the amplifier crossover frequency. r f is the feedback resistor. c s is the source capacitance including the photodiode and the board parasitic. c m is the common-mode capacitance of the amplifier. c d is the differential capacitance of the amplifier. the value of c f that produces f (45) can be shown to be cr f dm s f fr ccc c ??? ?? ? 2 (15) the frequency response shows less peaking if bigger c f values are used. the preamplifier output noise over frequency is shown in figure 51. ven (c f + c s + c m + c d )/c f voltage noise (nv/ hz) frequency (hz) noise due to amplifier ven f 2 f 3 f 1 r f noise f 1 = 1 2 r f (c f + c s + c m + c d ) f 2 = 1 2 r f c f f 3 = f cr (c f + c s + c m + c d )/c f 07756-043 figure 51. photodiode voltage noise contributions
ada4817- 1/ada4817 - 2 data sheet rev. b | page 20 of 28 45 40 35 30 25 20 15 10 5 0 ?5 0.1 1 10 100 1000 magnitude (db) frequency (mhz) 07756-051 g = 63v/v r l = 100 v s = 10v v out = 6v p-p figure 52 . photodiode preamp frequency response the pole in the loop transmission translates to a zero in the noise gain of the amplifier , leading to an amplification of the input voltage noise over frequency. the loop transmission zero introduced by c f limits the amplification. the noise gain bandwidth extends past the pre - amp signal bandwidth and is eventually rolled off by the decreasing loop gain of the amplifier. the current equivalent noise from the inverting terminal is typically negligible for most applications. the innovative architecture used in the ad a4817 - 1/ada4817 - 2 makes balancing both inputs unnecessary, as opposed to traditional fet input amplifiers. therefore, minimizing the impedance seen from the noninverting terminal to ground at all frequencies is critical for optimal noise performance. inte grating the square of the output voltage noise spectral density over frequency and then taking the square root allows users to obtain the total rms output noise of the preamp. table 9 summarizes approximations for the amplifier and feedback and source resistances. noise components for an example preamp with r f = 50 k?, c s = 30 pf, and c f = 0.5 pf (bandwidth of about 6.4 mhz) are also listed. table 9 . rms noise contributions of photodiode preamp contributor expression rms noise with r f = 5 0 k , c s = 30 p f, c f = 0.5 pf r f 57 . 1 4 2 f r kt f 94 v ven amp 57 . 1 3 + + + f c c c c c ven f f d m s 777.5 v i en amp 57 . 1 2 f r ien f 0.4 v 783 v ( total )
data sheet ada4817- 1/ada4817 - 2 rev. b | page 21 of 28 high speed jfet inpu t instrumentation amplifier figure 53 shows an example of a high speed ins trumentation amplifier with a high input impedance using the ada4817 - 1/ ada4817 - 2. the dc transfer function is ( ) ? ? ? ? ? ? ? ? + ? = g f p n out r r v v v 2 1 (16) for g = 1, it is recommended that the feedback resistors for the two preamps be set to 0 ? and the gain resistor be open. the system bandwidth for g = 1 is 400 mhz. for gains higher than 2, the bandwidth is set by the preamp, and it can be approximated by in - amp ?3 db = (f cr r g )/(2 r f ) common - mode rejection of the in - amp is primarily det ermined by the match of resistor ratios, r1:r2 to r3:r4. it can be estimated by ( ) ( ) 2 1 1 2 1 + ? = cm o v v (17) the summing junction impedance for the preamps is equal to r f || 0.5(r g ). keep this value relatively low to improve the bandwidth response like in the previous example. v cc v ee 10f 0.1f 10f 0.1f r s1 v n r2 350? v p ada4817-1 v o r g v cc v ee v cc v ee r4 350? r s2 10f 0.1f 10f 0.1f r1 350? r3 350? r f = 500? r f = 500? 10f 0.1f 10f 0.1f 07756-050 ada4817-2 u1 ada4817-2 u2 figure 53 . high speed instrumentation amplifier
ada4817-1/ada4817-2 data sheet rev. b | page 22 of 28 active low-pass filter (lpf) active filters are used in many applications such as antialiasing filters and high frequency communication if strips. with a 410 mhz gain bandwidth product and high slew rate, the ada4817-1/ada4817-2 is an ideal candidate for active filters. moreover, thanks to the low input bias current provided by the fet stage, the ada4817-1/ada4817-2 eliminate any dc errors. figure 54 shows the frequency response of 90 mhz and 45 mhz lpfs. in addition to the bandwidth requirements, the slew rate must be capable of supporting the full power bandwidth of the filter. in this case, a 90 mhz bandwidth with a 2 v p-p output swing requires at least 870 v/s. this performance is achievable at 90 mhz only because of the wide bandwidth and high slew rate of the ada4817-1/ada4817-2. the circuit shown in figure 55 is a 4-pole, sallen-key, low-pass filter (lpf). the filter comprises two identical cascaded sallen- key lpf sections, each with a fixed gain of g = 2. the net gain of the filter is equal to g = 4 or 12 db. the actual gain shown in figure 54 is 12 db. this does not take into account the output voltage being divided in half by the series matching termination resistor, r t , and the load resistor. setting the resistors equal to each other greatly simplifies the design equations for the sallen-key filter. to achieve 90 mhz the value of r should be set to 182 . however, if the value of r is doubled, the corner frequency is cut in half to 45 mhz. this would be an easy way to tune the filter by simply multiplying the value of r (182 ) by the ratio of 90 mhz and the new corner frequency in megahertz. figure 54 shows the output of each stage of the filter and the two different filters corresponding to r = 182 and r = 365 . it is not recommended to increase the corner frequency beyond 90 mhz due to bandwidth and slew rate limitations unless unity-gain stages are acceptable. resistor values are kept low for minimal noise contribution, offset voltage, and optimal frequency response. due to the low capacitance values used in the filter circuit, the pcb layout and minimization of parasitics is critical. a few picofarads can detune the corner frequency, f c , of the filter. the capacitor values shown in figure 55 actually incorporate some stray pcb capacitance. capacitor selection is critical for optimal filter performance. capacitors with low temperature coefficients, such as npo ceramic capacitors and silver mica, are good choices for filter elements. 15 ?42 100k 1g frequency (hz) magnitude (db) 12 9 6 3 0 ?3 ?6 ?9 ?12 ?15 ?18 ?21 ?24 ?27 ?30 ?33 ?36 ?39 1m 10m 100m 07756-062 out2, f = 90mhz out1, f = 90mhz out1, f = 45mhz out2, f = 45mhz figure 54. low-pass filter response u1 c1 3.9pf c2 5.6pf r r t 49.9 ? r r1 348 ? r r2 348 ? r t 49.9 ? +in1 ?5v +5v 0.1 f 0.1 f 10 f 10 f u2 c3 3.9pf c4 5.6pf r r3 348 ? r4 348 ? ?5v +5v 0.1 f 0.1 f 10 f 10 f out2 07756-054 out1 figure 55. 4-pole sallen-key low-pass filter (ada4817-2)
data sheet ada4817- 1/ada4817 - 2 rev. b | page 23 of 28 0.15 ?0.15 time (5ns/div) voltage (v) 0.10 0.05 0 ?0.05 ?0.10 45mhz 90mhz 07756-063 figure 56 . small signal transient response (low - pass filter ) 1.2 ?1.2 time (5ns/div) voltage (v) 0.8 0.4 0 ?0.4 ?0.8 45mhz 90mhz 07756-064 figure 57 . large sign al transient response (low - pass filter )
ada4817-1/ada4817-2 data sheet rev. b | page 24 of 28 outline dimensions 1 exposed pa d (bottom view) 0.50 bsc pin 1 indicator 0.50 0.40 0.30 top view 12 max 0.70 max 0.65 typ 0.90 max 0.85 nom 0.05 max 0.01 nom 0.20 ref 1.89 1.74 1.59 4 1.60 1.45 1.30 3.25 3.00 sq 2.75 2.95 2.75 sq 2.55 5 8 pin 1 indicator seating plane 0.30 0.23 0.18 0.60 max 0.60 max for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 04-04-2012-a figure 58. 8-lead lead frame chip scale package [lfcsp_vd] 3 mm 3 mm body, very thin, dual lead (cp-8-2) dimensions shown in millimeters compliant to jedec standards ms-012-a a 06-02-2011-b 1.27 0.40 1.75 1.35 2.29 2.29 0.356 0.457 4.00 3.90 3.80 6.20 6.00 5.80 5.00 4.90 4.80 0.10 max 0.05 nom 3.81 ref 0.25 0.17 8 0 0.50 0.25 45 coplanarity 0.10 1.04 ref 8 1 4 5 1.27 bsc s eating plane for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. bottom view top view 0.51 0.31 1.65 1.25 figure 59. 8-lead standard small outlin e package with exposed pad [soic_n_ep] (rd-8-1) dimensions shown in millimeters and (inches)
data sheet ada4817-1/ada4817-2 rev. b | page 25 of 28 compliant to jedec standards mo-220-wggc-3. 1 0.65 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 0.50 0.40 0.30 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator 0.35 0.30 0.25 2.40 2.35 sq 2.30 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 07-18-2012-b figure 60.16-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-16-20) dimensions shown in millimeters ordering guide model 1 temperature range package description pack age option ordering quantity branding ada4817-1acpz-r2 C40c to +105c 8-lead lfcsp_vd cp-8-2 250 h1f ada4817-1acpz-rl C40c to +105c 8-lead lfcsp_vd cp-8-2 5,000 h1f ada4817-1acpz-r7 C40c to +105c 8-lead lfcsp_vd cp-8-2 1,500 h1f ada4817-1acp-ebz evaluation board for 8-lead lfcsp ada4817-1ardz C40c to +105c 8-lead soic_n_ep rd-8-1 1 ada4817-1ardz-rl C40c to +105c 8-lead soic_n_ep rd-8-1 2,500 ada4817-1ardz-r7 C40c to +105c 8-lead soic_n_ep rd-8-1 1,000 ADA4817-1ARD-EBZ evaluation board for8-lead soic ada4817-2acpz-r2 C40c to +105c 16-lead lfcsp_wq cp-16-20 250 ada4817-2acpz-rl C40c to +105c 16-lead lfcsp_wq cp-16-20 5,000 ada4817-2acpz-r7 C40c to +105c 16-lead lfcsp_wq cp-16-20 1,500 ada4817-2acp-ebz evaluation board for16-lead lfcsp 1 z = rohs compliant part.
ada4817- 1/ada4817 - 2 data sheet rev. b | page 26 of 28 notes
data sheet ada4817- 1/ada4817 - 2 rev. b | page 27 of 28 notes
ada4817- 1/ada4817 - 2 data sheet rev. b | page 28 of 28 notes ? 2008 C 2013 analog devices, inc. all rights reserved. trademarks and register ed trademarks are the property of their respective owners. d07756 - 0- 5/13(b)

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